This application contains subject matter similar to subject matter disclosed in U.S. patent application Ser. No. 09/812,695, filed on Mar. 21, 2001, now U.S. Pat. No. 6,376,343 and Ser. No. 09/813,308, filed on Mar. 21, 2001.
The present invention relates to a method of manufacturing semiconductor devices, e.g., high-density integrated circuit (xe2x80x9cICxe2x80x9d) semiconductor devices exhibiting reliable, high quality, adherent, low resistance, well-aligned contacts to source, drain, and gate regions of active devices, such as MOS and CMOS transistors formed in or on a semiconductor substrate, by utilizing self-aligned, metal silicide (xe2x80x9csalicidexe2x80x9d) processing methodology. The present invention enjoys particular utility in the manufacture of high-density integration semiconductor devices, including multi-level devices, having design rules of 0.18 xcexcm and below, e.g., 0.15 xcexcm and below.
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) devices necessitate design rules of 0.18 xcexcm and below, such as 0.15 xcexcm and below, with increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction in feature sizes, e.g., of source, drain, and gate regions of transistors formed in or on a common semiconductor substrate, challenges the limitations of conventional contact and interconnection technology, including conventional photo-lithographic, etching, and deposition techniques.
As a result of the ever-increasing demand for large-scale and ultra small-dimensioned IC devices, self-aligned techniques have become the preferred technology for forming such devices in view of their simplicity and capability of high-density integration. As device dimensions decrease in the deep sub-micron range, both vertically and laterally, many problems arise, especially those caused by an increase in the sheet resistance of the contact areas to the source and drain regions and junction leakage as junction layer thickness decreases. To overcome this problem, the use of self-aligned, highly electrically conductive metal silicides, i.e., xe2x80x9csalicidesxe2x80x9d (derived from Self-ALIgned-siliCIDE), has become commonplace in the manufacture of IC semiconductor devices comprising, e.g., MOS type transistors. Another technique employed in conjunction with metal suicide technology is the use of lightly-doped, shallow-depth source and drain extensions formed just at the edge of the gate region, while more heavily-doped source and drain regions, to which ohmic contact is to be provided, are laterally displaced away from the gate by provision of sidewall spacers on opposing sides of the gate electrode.
Salicide processing involves deposition of a metal that forms an intermetallic compound with silicon (Si), but does not react with silicon oxides, nitrides, or oxynitrides under normal processing conditions. Metals commonly employed in salicide processing include platinum (Pt), titanium (Ti), nickel (Ni), and cobalt (Co), each of which forms very low resistivity phases with Si, e.g., PtSi2, TiSi2, NiSi, and CoSi2. In practice, the metal is deposited in a uniform thickness over all exposed surface features of a Si wafer, preferably by means of physical vapor deposition (xe2x80x9cPVDxe2x80x9d) process, e.g., sputtering from an ultra-pure target utilizing an ultra-high vacuum, multi-chamber DC magnetron sputtering system. In MOS transistor formation, deposition is generally performed after both gate etch and after source/drain formation. After deposition, the metal layer blankets the top surface of the gate electrode, typically formed of a heavily-doped polysilicon, the silicon oxide, nitride, or oxynitride sidewall spacers on the opposing side surfaces of the gate electrode, the silicon oxide isolation regions formed in the Si substrate between adjacent active device regions, and the exposed surfaces of the substrate where the source and drain regions are to be formed or will subsequently be formed. As a result of thermal processing, e.g., a rapid thermal annealing (xe2x80x9cRTAxe2x80x9d), the metal layer reacts with underlying Si to form electrically conductive metal silicide layer portions on the top surface of the polysilicon gate electrode and on the exposed surfaces of the substrate where source and drain regions are or will be formed. Unreacted portions of the metal layer, e.g., on the silicon oxide, nitride, or oxynitride sidewall spacers and the silicon oxide isolation regions, are then removed, as by a wet chemical etching process selective to the metal silicide portions. In some instances, e.g., with Co, a first RTA step may be performed at a relatively lower temperature in order to form first-phase CoSi, which is then subjected to a second RTA step performed at a relatively high temperature to convert the first-phase CoSi to second-phase, lower resistivity CoSi2.
A number of different techniques and fabrication processes have been either proposed or utilized for forming MOS transistors and/or CMOS devices according to salicide methodology. Referring to FIGS. 1(A)-1(I), shown therein, for illustrative purposes only, is an example of a typical salicide-based process according to conventional processing technology. In a preliminary step, shown in FIG. 1(A), a silicon (Si) or Si-based substrate 102, typically a monocrystalline Si wafer of one conductivity type (p or n) or comprising a well region of one conductivity type formed therein, is processed, as by conventional techniques such as formation of field oxide regions, local oxidation of silicon (xe2x80x9cLOCOSxe2x80x9d), shallow trench isolation (xe2x80x9cSTIxe2x80x9d), etc., to define a plurality of electrically separated regions. In the illustrated embodiment, shallow isolation trenches 216 (only one is shown for illustrative simplicity) are formed in a surface portion of substrate 102, as by isotropic etching utilizing wet chemical etching techniques or by anisotropic etching utilizing dry etching techniques, e.g., reactive plasma etching. Trenches 216 are then filled with an oxide 218 layer, such that an edge 220 of the oxide 218 contacts the substrate 102 at locations where doped regions will subsequently be formed within the substrate 102. (Trench 216 and oxide layer 218 are not shown in the following drawing figures for illustrative simplicity).
Referring now to FIG. 1(B), a thin gate oxide (insulator) layer 104, typically a silicon oxide layer about 15-50 xc3x85 thick, is formed on the upper surface of substrate 102, e.g., by thermal oxidation at temperatures of from about 700 to about 1,000xc2x0 C. in an oxidizing atmosphere. After formation of the gate oxide layer 104, a blanket layer of undoped polysilicon 106 is deposited on the gate oxide layer 104, for example, by low pressure chemical vapor deposition (xe2x80x9cLPCVDxe2x80x9d). If desired, polysilicon layer 106 can be treated to retard diffusion of boron (B) atoms therethrough, as by implantation with nitrogen (N2) ions, symbolically indicated in the figure by arrows 160.
Adverting to FIG. 1(C), a continuous photoresist layer 110 is then deposited on the polysilicon layer 106, and the photoresist layer 110 is selectively irradiated utilizing photolithographic masking techniques and developed, followed by removal of the selectively irradiated portions thereof to expose portions of the polysilicon layer 106 which are to be removed to define a gate electrode. As shown in FIG. 1(D), the exposed portions of polysilicon layer 106 and the respective underlying portions of the thin gate oxide layer 104 are removed, as by anisotropic etching, to form polysilicon gate electrode 112 having vertically opposed sidewalls or edges 114, 116.
With reference to FIG. 1(E), the remaining portion of the photoresist layer 110 is then stripped from the upper surface of the polysilicon gate electrode 112 and a pair of shallow-depth, source and drain extension regions 130, 132 are formed in substrate 102 by an ion implantation 128 (xe2x80x9cextension implantxe2x80x9d) process, utilizing the polysilicon gate electrode 112 as an implantation mask. Source and drain extension regions 130, 132 thus are formed in a self-aligned manner and extend within the substrate 102 to immediately adjacent the edges of sidewalls 114, 116 of the gate electrode/gate oxide layer stack 112/104. The implanted ions may comprise an n-type dopant, e.g., As ions, if an NMOS is desired to be formed, or a p-type dopant, e.g., B-containing ions, if a PMOS is to be formed. By way of illustration only, n-type source and drain extension regions 130, 132 having a shallow-depth of from about 100 to about 200 xc3x85 and a doping of from about 1xc3x971020 to about 1xc3x971021 da/cm3 may be formed in crystalline Si by implanting As ions at a dosage of from about 1xc3x971015 to about 2xc3x971015 da/cm2 and energies of from about 2 to about 5 KeV.
Referring now to FIG. 1(F), tapered width sidewall spacers 162, 164 comprised of an insulative material, typically a silicon oxide, nitride, or oxynitride, are then formed on the surfaces of sidewalls 114, 116 of the gate electrode/gate oxide layer stack 112/104. Typically, the tapered width sidewall spacers 162, 164 are formed by a process comprising forming, as by a suitable conventional deposition method, a blanket layer of the insulative material covering all exposed surface portions of the substrate 102 as well as all exposed surfaces of the various features formed therein or thereon, including, inter alia, the opposing sidewall surfaces 114, 116 and top surface of the polysilicon gate electrode 112. The thickness of the blanket insulative layer is selected so as to provide tapered sidewall spacers 162, 164 having a desired width profile. The blanket insulative layer is then subjected to an anisotropic etching process, e.g., plasma etching in a fluorine-containing plasma, for selectively removing the laterally extending portions thereof and forming the tapered width sidewall spacers 162, 164. Following the formation of the tapered sidewall spacers 162, 164, a pair of deeper source and drain regions 200, 202 are formed, as by a xe2x80x9cmain implantxe2x80x9d ion implantation 204 process utilizing the tapered sidewall spacers 162, 164 as implantation masks, generally within the portions of substrate 102 where the shallow-depth, source and drain extension regions 130, 132 were previously formed. As shown in the figure, the deeper source and drain regions 200, 202 formed by the xe2x80x9cmain implantxe2x80x9d process extend beyond the depth of source and drain extension regions 130, 132, except at the portions of the latter regions underlying the sidewall spacers 162, 164. By way of illustration only, according to conventional practice, typical As implantation conditions for forming source and drain regions 200, 202 of a Si wafer-based NMOS transistor having a peak As n-type dopant concentration of from about 1xc3x971020 to about 1xc3x971021 da/cm3 at a depth of from about 200 to about 400 xc3x85 below the surface of the Si wafer include dosages of from about 3xc3x971015 to about 6xc3x971015 da/cm2 and energies of from about 10 to about 40 KeV.
With reference to FIG. 1(G), in a following step, a blanket layer 140 of a metal, typically Pt, Co, Ni, or Ti, is formed, as by a PVD process such as DC sputtering, to cover all exposed surfaces of the thus-formed structure. The thickness of the metal layer deposited in this step depends upon several factors, including, inter alia, the particular selected metal, its Si consumption ratio, and desired thickness (hence resistance) of the resultant metal silicide.
Adverting to FIG. 1(H), following metal layer 140 deposition, a thermal treatment, typically RTA, is performed at a temperature and for an interval sufficient to convert at least a portion of the thickness of metal layer 140 to the corresponding electrically conductive metal silicide 142, e.g., PtSi2, CoSi2, NiSi, or TiSi2. Since the metal silicide 142 forms only where the metal layer 140 is in contact with underlying Si of Si substrate 102, the unreacted portions of the metal layer 140 formed over the sidewall spacers 162, 164 and oxide-filled isolation trenches 216 (not shown in the figure for simplicity) are selectively removed, as by a wet chemical etch process, to yield the structure shown in FIG. 1(I), which structure can then undergo further processing for contact formation to the source/drain regions and gate electrode.
When Ni is utilized as the metal layer 140, conversion of Ni to NiSi may be accomplished by means of a one-step thermal process, typically RTA performed at temperatures of from about 350 to about 750xc2x0 C., for example, in a N2 atmosphere at 550xc2x0 C. for about 40 sec. The formation of NiSi commences at about 250xc2x0 C., when the Ni layer 140 reacts with the Si substrate 102 to form Ni2Si. With increase in reaction time or temperature to above about 300xc2x0 C., the Ni2Si undergoes further reaction with the Si substrate 102 to form NiSi layer 142. By way of illustration only, a Ni layer 140 from about 100 to about 200 xc3x85 thick may be subjected to silicidation reaction with the Si substrate 102 (as described above) to form a NiSi layer 142 extending to a depth below the Si substrate 102 of from about 180 to about 360 xc3x85. Removal of any unreacted portions of Ni layer 140 can be accomplished, for example, by etching with a 2:1 H2SO4/H2O2 mixture at a temperature of about 100xc2x0 C. An aqueous mixture of NH4OH and H2O2 may be utilized for stripping other unreacted metals, i.e., Co, Ti, Pt.
Referring now to FIG. 2, a problem frequently encountered with salicide processing sequences, such as the one described supra, is the formation of metal silicide layers 142 wherein the lower surfaces 142L thereof are rough at the metal silicide/Si interfaces 143, which roughness can disadvantageously result in penetration of the underlying silicon substrate 102 by the metal silicide layer 142. In particular, such penetration, or xe2x80x9cspikingxe2x80x9d of the Si substrate 102 in the regions below the source and drain regions 200, 202 can cause local electrical punch-through of the source and drain junctions 204, 206 for example, as indicated by 204LS, 206LS, respectively, in the figure, thereby resulting in junction leakage. While the effect of local electrical punch-through or spiking is significant when a metal having a high Si consumption ratio is utilized, e.g., Co, silicide/Si interface roughness resulting in local electrical punch-through can also result from incompatibility between a particular metal and a particular dopant species utilized for forming the source and drain regions. In this regard, a notable (but not exclusive) example is the incompatibility of Ni as the metal and As atoms/ions as the n-type dopant species for Si, e.g., in the formation of Si-based NMOS transistors and CMOS devices.
Specifically, the presence of significant amounts of As in NiSi layers on source/drain regions of NMOS transistors and CMOS devices results in a substantial amount or degree of roughness at the NiSi/Si interface, leading to increased junction leakage due to local electrical punch-through or xe2x80x9cspikingxe2x80x9d of the source/drain junctions as described above. Further, since As atoms or ions tend to be rejected, (i.e., expelled) from NiSi films, they can accumulate in the vicinity of the NiSi/Si interface and below, thereby exacerbating the problem of local junction electrical punch-through and disadvantageously altering the dopant concentration vs. depth profile so as to degrade transistor properties. Such incompatibility with NiSi is peculiar to As (i.e., it is not observed with other n-type dopant species) and is particularly troublesome in that (1) As is otherwise advantageous vis-xc3xa1-vis the other common n-type dopant species (i.e., phosphorus (P) and antimony (Sb)) utilized in forming ion implanted, shallow junction source and drain regions in high-speed, Si-based NMOS transistors and CMOS devices, in view of its low diffusivity (with respect to P) and high solid solubility (with respect to Sb); and (2) NiSi is a preferred electrically conductive, metal silicide material vis-xc3xa1-vis other metal silicides (CoSi2, TiSi2, PtSi2, etc.) in view of its rapid formation at relatively low temperatures (350-600xc2x0 C.) in a one-step RTA process, lack of line width dependence, low resistivity, low Si consumption ratio, and increased process flexibility.
Accordingly, there exists a clear need for improved methodology for simple, reliable, and rapid formation of metal suicide layers for use in the manufacture of semiconductor IC devices, e.g., in the formation of electrically conductive contact layers to dopant-containing source and drain regions in MOS transistors and/or CMOS devices, which methodology avoids the drawbacks associated with the conventional salicide techniques and methodologies and provides, inter alia, high-quality MOS transistors and/or CMOS devices exhibiting reduced junction leakage and improved transistor characteristics and properties.
The present invention, wherein the peak of the concentration vs. depth profile of a conductivity-determining dopant species introduced into a semiconductor substrate, e.g., for forming source and drain regions therein, is shifted to a lower than conventional depth in the substrate which is displaced from the depth to which a metal silicide is subsequently formed, thereby reducing the concentration of the dopant species in the metal silicide below a threshold level at which adverse affects are observed, eliminates, or at least substantially reduces, the disadvantageous interaction(s) between the metal silicide and the dopant species leading to roughness of the metal silicide/silicon interface and local electrical punch-through of the source/drain junctions. The inventive methodology thus effectively addresses and solves the need for improved methodology for the manufacture of high-quality MOS transistors and/or CMOS devices with reduced junction leakage due to local electrical punch-through of the source and drain junctions arising from the rough interface. Further, the methodology provided by the present invention enjoys diverse utility in the manufacture of numerous and various types of semiconductor devices and/or components employing salicide technology.
An advantage of the present invention is an improved method for forming an electrically conductive metal silicide layer on a Si-based semiconductor substrate.
Another advantage of the present invention is an improved method for forming an electrically conductive NiSi layer on an As-doped, n-type region of a Si semiconductor substrate.
Yet another advantage of the present invention is an improved method of manufacturing a Si-based NMOS transistor or CMOS device including electrically conductive NiSi layers formed in contact with As-doped, n-type source and drain regions.
Still another advantage of the present invention is improved Si-based semiconductor devices comprising at least one electrically conductive NiSi layer formed in contact with an As-containing, n-type Si region.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device, which method comprises the steps of:
(a) providing a silicon (Si)-based semiconductor substrate having a surface;
(b) introducing a first conductivity type first dopant into at least one selected portion of the substrate, such that the concentration vs. depth profile of the first dopant has a peak at a first depth below the substrate surface;
(c) introducing a second conductivity type second dopant into the at least one selected portion of the substrate, such that the concentration vs. depth profile of the second dopant has a peak at a second depth below the substrate surface, the second depth being greater than the first depth, whereby the first depth is controlled/limited by the second depth;
(d) forming a metal layer on the substrate surface overlying the at least one selected portion of the substrate;
(e) reacting the metal layer with the at least one selected portion of the Si-based substrate to form a layer of an electrically conductive metal suicide extending below the substrate surface to a third depth which is less than the first depth, thereby eliminating or at least substantially reducing roughness of the at least one interface between the metal silicide layer and the at least one selected portion of the Si substrate by minimizing the concentration of the first dopant in the metal suicide layer.
According to embodiments of the present invention, step (b) comprises implanting the first conductivity type first dopant, e.g., implanting an n-type first dopant comprising at least one member selected from the group consisting of arsenic (As), phosphorus (P), and antimony (Sb).
According to particular embodiments of the present invention, step (b) comprises implanting As ions as the n-type first dopant.
According to further embodiments of the present invention, step (c) comprises implanting a p-type second dopant, e.g., step (c) comprises implanting boron (B)-containing ions as the p-type second dopant; and the method comprises either performing step (b) followed by step (c) or performing step (c) followed by step (b).
According to still further embodiments of the present invention, step (d) comprises forming a metal layer comprising at least one metal selected from the group consisting of: nickel (Ni), cobalt (Co), titanium (Ti), and platinum (Pt).
According to particular embodiments of the present invention, step (d) comprises forming a Ni layer; and step (e) comprises forming an electrically conductive NiSi layer.
According to yet further embodiments of the present invention, step (b) comprises implanting As n-type dopant ions as the first dopant for forming n-type source and drain regions in selected portions of the substrate as part of a process for forming an NMOS transistor or CMOS device; step (c) comprises implanting boron (B)-containing p-type dopant ions as the second dopant; step (d) comprises forming a Ni layer overlying at least the selected portions of the substrate; and step (e) comprises reacting the Ni layer with the Si-based substrate to form a layer of electrically conductive nickel silicide (NiSi).
According to particular embodiments of the present invention, step (a) comprises providing a monocrystalline Si wafer substrate; step (b) comprises implanting As ions as said first dopant ions at a dosage and energy such that the first depth is from about 250 to about 500 xc3x85 below said substrate surface; step (c) comprises implanting B-containing second dopant ions at a dosage and energy such that the second depth is from about 450 to about 700 xc3x85 below the substrate surface; step (d) comprises forming a Ni layer having a thickness of from about 100 to about 200 xc3x85; and step (e) comprises reacting the Ni layer with the Si substrate to form an electrically conductive NiSi layer extending to the third depth below the substrate surface of from about 180 to about 360 xc3x85, wherein: step (b) comprises implanting As ions at a dosage of from about 3xc3x971015 to about 6xc3x971015 da/cm2 and energy of from about 35 to about 85 KeV; step (c) comprises implanting B-containing ions at a dosage of from about 3xc3x971013 to about 1xc3x971014 da/cm2 and an energy of from about 14 to about 22 KeV; and step (d) comprises heating the Ni in an inert atmosphere at a temperature of from about 300 to about 550xc2x0 C. for from about 30 to about 60 sec.
According to another aspect of the present invention, a method of manufacturing an NMOS transistor or CMOS semiconductor device comprises the steps of:
(a) providing a Si semiconductor substrate having a surface;
(b) forming a thin gate insulator layer in contact with the substrate surface;
(c) forming an electrically conductive gate electrode on a portion of the thin gate insulator layer, the gate electrode comprising first and second opposing side surfaces and a top surface;
(d) forming a pair of shallow-depth, n-type source and drain extension regions in portions of the substrate, each of the source and drain extension regions extending laterally to beneath an edge of a respective one of the first and second opposing side surfaces of the gate electrode;
(e) forming sidewall spacers composed of an insulating material on each of the first and second opposing side surfaces of the gate electrode;
(f) forming, by implantation of As n-type dopant ions utilizing the sidewall spacers as an implantation mask, a pair of deeper, n-type source and drain regions in the source and drain regions formed in step (d), such that the concentration vs. depth profile of the implanted As ions has a peak at a first depth below the substrate surface;
(g) implanting B-containing p-type dopant ions into the pair of n-type source and drain regions utilizing the sidewall spacers as an implantation mask, such that the concentration vs. depth profile of the implanted B-containing dopant ions has a peak at a second depth below the substrate surface, the second depth being greater than the first depth, whereby the first depth is controlled/limited by the second depth;
(h) forming a layer of Ni on the substrate surface overlying at least the pair of source and drain regions; and
(i) reacting the Ni layer with the Si semiconductor substrate to form an electrically conductive NiSi layer extending into the pair of source and drain regions for a third depth below the substrate surface, the third depth being less than the first depth, thereby eliminating or at least substantially reducing roughness of the interfaces between the NiSi layers and the As-doped source and drain regions by minimizing the concentration of As ions in the NiSi layer.
According to embodiments of the present invention, the method comprises either performing step (f) followed by step (g), or performing step (g) followed by step (f).
According to particular embodiments of the present invention, step (d) comprises forming the pair of n-type source and drain extension regions at a shallow depth of from about 100 to about 200 xc3x85; step (f) comprises implanting the As dopant ions at a dosage and energy such that the first depth is from about 250 to about 500 xc3x85 below the substrate surface; step (g) comprises implanting the B-containing dopant ions at a dosage and energy such that the second depth is from about 450 to about 700 xc3x85 below the substrate surface; step (h) comprises forming a Ni layer having a thickness of from about 100 to about 260 xc3x85; and step (i) comprises reacting the Ni layer with the Si substrate to form a NiSi layer extending to the third depth below the substrate surface of from about 180 to about 360 xc3x85; wherein step (d) comprises implanting As ions at a dosage of from about 1xc3x971015 to about 2xc3x971015 da/cm2 and energy of from about 2 to about 5 KeV; step (f) comprises implanting As ions at a dosage of from about 3xc3x971015 to about 6xc3x971015 da/cm2 and energy of from about 35 to about 85 KeV; step (g) comprises implanting B-containing ions at a dosage of from about 3xc3x971013 to about 1xc3x971014 da/cm2 and energy of from about 14 to about 22 KeV; and step (i) comprises heating the Ni layer in an inert atmosphere at a temperature of from about 300 to about 550xc2x0 C. for from about 30 to about 60 sec.
According to yet another aspect of the present invention, a semiconductor device comprises:
(a) a Si semiconductor substrate having a surface;
(b) at least one n-type doped region formed in the substrate, the n-type doped region comprising implanted As n-type dopant ions, the concentration vs. depth profile of the implanted As ions having a peak at a first depth below the substrate surface;
(c) an electrically conductive NiSi layer extending from the substrate surface into the at least one n-type, As-doped region to a second depth below the substrate surface, the second depth being less than the first depth; and
(d) a p-type doped region formed in the substrate beneath the at least one n-type doped region, the p-type doped region comprising implanted B-containing dopant ions, the concentration vs. depth profile of the implanted B-containing dopant ions having a peak at a third depth below the substrate surface, wherein the second depth being less than the first depth eliminates or at least substantially reduces roughness at the interface between the NiSi layer and the As-doped region by minimizing the concentration of As ions in the NiSi layer, and the third depth being greater than the first depth controls/limits the first depth.
According to embodiments of the present invention, the at least one n-type As-doped region is a source or drain region of an NMOS transistor or a CMOS device.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.